1. Field of the Invention
This invention relates generally to digital logic circuits and more particularly relates to a MOSFET source-coupled logic circuit which is faster, can be implemented with fewer transistors and avoids double-ended or complementary differential logic.
2. Description of the Related Art
This invention relates to source-coupled logic (SCL) which is a functional derivative of emitter-coupled logic (ECL). ECL is widely recognized as having the characteristics of high speed (low propagation delay) and low power supply noise generation. The SCL of the prior art succeeds at maintaining and improving the low noise characteristics of this architecture but does not fulfill the promise of high speed that one would expect from a current-mode logic. In addition, it uses a differential form of logic that is not as flexible and easy-to-use as a reference controlled or "single-ended" logic. The SCL disclosed here has the desired high speed properties and maintains the ease of use that is a property of reference controlled ECL. In addition, the reference controlled SCL of this invention provides new capabilities that make it even more flexible than ECL in generating logical switching functions.
A schematic diagram of a generic ECL inverter/buffer circuit is shown in FIG. 1. For clarity, the pull-down resistors that are required at the outputs have been omitted. Descriptions of the operation of this circuit have been widely disseminated (including U.S. Pat. No. 3,259,761 and [1]). In essence, the input signal, V.sub.IN, is compared with a reference voltage, V.sub.BB, by a differential pair of matched bipolar junction transistors (BJTs), Q1 and Q2. The relative values of V.sub.IN and V.sub.BB determine whether a bias current common to the emitters of Q1 and Q2, I.sub.EE, is directed to one of two resistors, R1 or R2. When V.sub.IN &lt;V.sub.BB, this bias current flows through transistor Q2 resulting in a voltage drop across resistor R2. This voltage is both buffered and level-shifted by an output emitter-follower transistor, Q4, resulting in a logic low voltage at the V.sub.O output. Simultaneously, the absence of any current flowing through R1 results in a logic high voltage at the inverting output, V.sub.O.sub..sub.-- .sub.N. When V.sub.IN &gt;V.sub.BB, the I.sub.EE bias current flows through transistor Q1 causing a voltage drop across resistor R1 rather than resistor R2. In this case, a low voltage, or logic 0, is developed at the inverting output, V.sub.O.sub..sub.-- .sub.N, while a high voltage, or logic 1, is developed at the non-inverting output, V.sub.O. A reference voltage, V.sub.BB, that is midway between the logic high and low voltages is supplied by an external bias circuit. A single bias circuit is usually shared by many ECL gate circuits. This bias circuit also regulates the value of I.sub.EE ; typically by employing another BJT.
The essential aspects of a differential SCL gate are shown in FIG. 2. (See U.S. Pat. No. 5,149,992 and [2-3].) The inverter/buffer shown here uses metal-oxide-semiconductor (MOS) field effect transistors (FETs) rather than BJTs but operation is similar. When V.sub.IN &lt;V.sub.IN.sub..sub.-- .sub.N, the common source bias current, I.sub.SS, flows through transistor M2 but not transistor M1 developing a low voltage at the non-inverting output, V.sub.O, and a high voltage at the inverting output, V.sub.O.sub..sub.-- .sub.N. When V.sub.IN &gt;V.sub.IN.sub..sub.-- .sub.N the opposite occurs: V.sub.O assumes a high, logic 1, voltage and V.sub.O.sub..sub.-- .sub.N assumes a low, logic 0, voltage. The logic input to this inverter/buffer gate consists of a pair differential of voltages, V.sub.IN and V.sub.IN.sub..sub.-- .sub.N, that each assume opposite states. While the use of two voltages to convey one signal can present several problems, it greatly simplifies the bias circuit. In fact, the bias circuit may be eliminated altogether if it is not necessary to closely regulate the value of I.sub.SS for optimum performance.
The circuit of FIG. 2 assumes the use of enhancement mode N-type MOSFETs which typically have a positive threshold voltage that is of the same magnitude as the forward voltage of the NPN BJTs used in ECL circuits. It is also possible to perform logical switching functions by substituting FETs which have a lower threshold voltage, or even a negative threshold voltage (i.e., depletion mode FETS). Such source-coupled FET logic (SCFL) gates (see U.S. Pat. No. 3,783,400 and [4-5]) typically employ one or more forward biased diodes between the output source-follower transistors and their respective gate output terminals to increase the amount of voltage level-shifting provided. Otherwise, the operation of a SCFL gate is the same as that of a SCL gate.
Applicant cites the following art: